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for free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. for small orders, phone 1-800-835-8769. general description the max1459 highly integrated analog-sensor signal conditioner is optimized for piezoresistive sensor calibra- tion and compensation with minimal external compo- nents. it includes a programmable current source for sensor excitation, a 3-bit programmable-gain amplifier (pga), a 128-bit internal eeprom, and four 12-bit dacs. achieving a total error factor within 1% of the sensor? repeatability errors, the max1459 compensates offset, offset temperature coefficient (offset tc), full-span output (fso), fso temperature coefficient (fsotc), and fso nonlinearity of silicon piezoresistive sensors. the max1459 calibrates and compensates first-order temperature errors by adjusting the offset and span of the input signal through digital-to-analog converters (dacs), thereby eliminating quantization noise. the max1459 allows temperature compensation via the external sensor, an internal temperature-dependent resistor, or a dedicated external temperature transduc- er. accuracies better than 0.5% can be achieved with low-cost external temperature sensors (i.e., silicon tran- sistor), depending on sensor choice. built-in testability features on the max1459 result in the integration of three traditional sensor-manufacturing operations into one automated process: ? pretest: data acquisition of sensor performance under the control of a host test computer. ? calibration and compensation: computation and storage (in an internal eeprom) of calibration and compensation coefficients computed by the test computer and downloaded to the max1459. ? final test operation: verification of transducer cali- bration and compensation without removal from the pretest socket. although optimized for use with piezoresistive sensors, the max1459 may also be used with other resistive sensors (i.e., accelerometers and strain gauges) with some additional external components. ________________________applications 4?0ma transmitters piezoresistive pressure and acceleration industrial pressure sensors load cells/wheatstone bridges strain gauges temperature sensors features highly integrated sensor signal conditioner for 2-wire, 4?0ma transmitters sensor errors trimmed using correction coefficients stored in internal eeprom eliminates the need for laser trimming and potentiometers compensates offset, offset tc, fso, fsotc, fso linearity programmable current source (0.1ma to 2.0ma) for sensor excitation fast signal-path settling time ( 1ms) accepts sensor outputs from +1mv/v to +40mv/v fully analog signal path internal or external temperature reference compensation automated pilot production (calibration/ compensation) system available write protection for eeprom data security pin configuration ordering information max1459 2-wire, 4?0ma smart signal conditioner ________________________________________________________________ maxim integrated products 1 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 sclk v dd nbias ck50 temp2 temp1 inm inp bdrive top view max1459 ssop cs dio amp+ we fsotc amp- ampout 12 11 9 10 v ss out tempin isrc 19-1619; rev 0; 1/00 * dice are tested at t a = +25?, dc parameters only. functional diagram appears at end of data sheet. evaluation kit available 20 ssop dice* 20 ssop pin-package temp. range 0? to +70? 0? to +70? -40? to +125? max1459aap max1459c/d max1459cap part for custom versions of the max1459, see the customization section at end of data sheet.
max1459 2-wire, 4?0ma smart signal conditioner 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage, v dd to v ss ......................................-0.3v to +6v all other pins ...................................(v ss - 0.3v) to (v dd + 0.3v) short-circuit duration, fsotc, out, bdrive ...........continuous continuous power dissipation (t a = +70?) 20-pin ssop (derate 8.00mw/? above +70?) ..........640mw operating temperature ranges max1459cap ......................................................0? to +70? max1459aap .................................................-40? to +125? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (v dd = +5v, v ss = 0, t a = +25?, unless otherwise noted.) parameter symbol min typ max units amplifier gain nonlinearity 0.01 %v dd input-referred offset tempco ?.5 ?/? input impedance r in 1 m ? output step response 2 ms common-mode rejection ratio cmrr 90 db input-referred adjustable offset range ?50 mv supply voltage v dd 4.5 5.0 5.5 v supply current i dd 2.0 2.5 ma input-referred adjustable full- span output (fso) range +1 to +40 mv/v differential signal gain range +41 to +230 v/v minimum differential signal gain +36 +41 +44 v/v differential signal gain tempco ?0 ppm/? output current range -0.45 0.45 (sink) (source) ma output noise 500 ? rms conditions (note 5) (notes 2, 3) 63% of final value selectable in eight steps t a = t min to t max from v ss to v dd at minimum gain (note 4) t a = t min to t max v out = (v ss + 0.25v) to (v dd - 0.25v) dc to 10hz (gain = 41, source impedance = 5k ? ) r nbias = 402k ? , v dd = 5.0v (note 1) output voltage swing v ss + 0.05 v dd - 0.05 v no load v ss + 0.25 v dd - 0.25 10k ? load general characteristics analog input (pga) analog output (pga) bridge current range i bdrive 0.1 0.5 2.0 ma bridge voltage swing v bdrive v ss + 1.3 v dd - 1.3 v i bdrive = 2ma reference input voltage range (isrc) v isrc v ss + 1.3 v dd - 1.3 v current source
electrical characteristics (continued) (v dd = +5v, v ss = 0, t a = +25?, unless otherwise noted.) max1459 2-wire, 4?0ma smart signal conditioner _______________________________________________________________________________________ 3 fso dac bit weight ? v isrc ? code 1.22 mv/bit fsotc dac bit weight ? v fsot ? code 0.6 mv/bit dac reference = v dd = 5.0v dac reference = v bdrive = 2.5v offset dac bit weight ? v out ? code 2.8 mv/bit offset tc dac bit weight ? v out ? code 1.4 mv/bit dac reference = v dd = 5.0v dac reference = v bdrive = 2.5v dac resolution 12 bits differential nonlinearity dnl ?.5 lsb parameter symbol min typ max units dac bit weight 9 mv/bit dac resolution 3 bits output voltage swing 0.2 4.0 v current drive -20 20 ? current source reference resistor r isrc 100 k ? fso trim resistor r ftc 100 k ? temperature-dependent resistor r temp 100 k ? conditions input referred, v dd = 5v (note 6) no load, v b = 5v v fsotc = 2.5v input common-mode range cmr v ss v dd v open-loop gain a v 60 db offset voltage (as unity-gain follower) -30 30 mv v in = v dd /2 output swing v ss + 0.05 v dd - 0.05 v no load output current ? ma digital-to-analog converters iro dac fsotc buffer (fsotc pin) internal resistors auxiliary op amp
max1459 2-wire, 4?0ma smart signal conditioner 4 _______________________________________________________________________________________ __________________________________________typical operating characteristics (v dd = +5v, v ss = 0, t a = +25?, unless otherwise noted.) 0 0.5 1.0 1.5 2.0 2.5 -40 40 60 020 -20 80 100 120 supply current vs. temperature max1459 toc01 temperature (?) supply current (ma) v out = 2.47v at +25? -40 40 60 020 -20 80 100 120 r temp vs. temperature max1459 toc02 temperature ( c) r temp ( ? ) 0 60 40 20 80 100 120 140 160 180 200 -40 40 60 020 -20 80 100 120 v out vs. temperature max1459 toc03 temperature ( c) v out (v) 0 1.5 1.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v out = 2.5v at +25 c v in = 56.5mv v out = 2.47v at +25 c v in = 0 note 1: excludes the sensor or load current. note 2: all electronics temperature errors are compensated together with sensor errors. note 3: the sensor and the max1459 must always be at the same temperature during calibration and use. note 4: this is the maximum allowable sensor offset. note 5: this is the sensor? sensitivity normalized to its drive voltage, assuming a desired full-span output of 4v and a bridge voltage of 2.5v. sensors smaller than +10mv/v require an auxiliary op amp. note 6: bit weight is ratiometric to v dd . electrical characteristics (continued) (v dd = +5v, v ss = 0, t a = +25?, unless otherwise noted.) i sink = 2ma v 0.5 v ol low-level output voltage i source = 1ma v 4 v oh high-level output voltage v 2 input hysteresis v 0.25 x v dd v il low-level input voltage v 0.75 x v dd v ih high-level input voltage conditions units min typ max symbol parameter digital pins
max1459 2-wire, 4?0ma smart signal conditioner _______________________________________________________________________________________ 5 temperature sensor terminal 1 temp1 16 temperature sensor terminal 2. r temp is a 100k ? temperature-dependent resistor with 4600ppm/? tempco. temp2 17 output voltage. out is a rail-to-rail output that can drive resistive loads down to 10k ? and capacitive loads up to 0.1?. out 11 negative power supply v ss 12 sensor excitation current output. the current source that drives the bridge. bdrive 13 positive sensor input. input impedance is typically 1m ? . rail-to-rail input range. inp 14 negative sensor input. input impedance is typically 1m ? . rail-to-rail input range. inm 15 auxiliary op amp negative input amp- 7 auxiliary op amp output ampout 8 input pin for an external temperature-dependent reference voltage for fsotc dac and otc dac. in the default mode, the max1459 uses the temperature-dependent bridge drive voltage as the fsotc dac and otc dac reference. tempin 9 current source reference. an internal 100k ? resistor (r isrc ) connects isrc to v ss (see functional diagram ). optionally, external resistors can be used in place of or in parallel with r ftc and r isrc . isrc 10 auxiliary op amp positive input amp+ 6 buffered full-span output temperature coefficient dac output. an internal 100k ? resistor (r ftc ) con- nects fsotc to isrc (see functional diagram ). optionally, external resistors can be used in place of or in parallel with r ftc and r isc . fsotc 5 write enable, dual-function input pin. used to enable eeprom erase/write operations. also used to set the dac refresh-rate mode. internally pulled to v dd with a 1m ? (typ) resistor. see the chip-select (cs) and write-enable (we) section. we 4 data input/output. used only during programming/testing. internally pulled to v ss with a 1m ? (typical) resistor. high impedance when cs is low. dio 3 positive power-supply input. connect a 0.1? capacitor from v dd to v ss . v dd 20 clock output, nominally 50khz ck50 18 chip current bias source. connect an external 402k ? ?% resistor between v dd and nbias. nbias 19 pin description 1 chip-select input. the max1459 is selected when this pin is high. when low, out and dio become high impedance. internally pulled to v dd with a 1m ? (typical) resistor. leave unconnected for normal operation. cs 2 data clock input. used only during programming/testing. internally pulled to v ss with a 1m ? (typical) resistor. data is clocked in on the rising edge of the clock. recommended sclk frequency is below 50khz. sclk pin function name rail-to-rail is a registered trademark of nippon motorola, ltd.
max1459 _______________detailed description the max1459 provides an analog amplification path for the sensor signal and a digital path for calibration and temperature correction. calibration and correction is achieved by varying the offset and gain of a program- mable-gain amplifier (pga) and by varying the sensor bridge current. the pga utilizes a switched-capacitor cmos technology, with an input-referred offset trim- ming range of ?3mv (9mv steps). an additional out- put-referred fine offset trim is provided by the offset dac (approximately 2.8mv steps). the pga provides eight gain values from +41v/v to +230v/v. the bridge current source is programmable from 0.1ma to 2ma. the max1459 uses four 12-bit dacs with calibration coefficients stored by the user in an internal 128-bit eeprom. this memory contains the following informa- tion as 12-bit-wide words: ? configuration register ? offset calibration coefficient ? offset temperature error compensation coefficient ? full-span output (fso) calibration coefficient ? fso temperature error compensation coefficient ? 24 user-defined bits for customer programming of manufacturing data (e.g., serial number and date) figure 1 shows a typical pressure-sensor output and defines the offset, full-scale, and fso values as a func- tion of voltage. fsotc compensation silicon piezoresistive transducers (prts) exhibit a large positive input resistance tempco (tcr) so that, while under constant current excitation, the bridge voltage (v bdrive ) increases with temperature. this depen- dence of v bdrive on the sensor temperature can be used to compensate the sensor temperature errors. prts also have a large negative full-span output sensi- tivity tempco (tcs) so that, with constant voltage exci- tation, fso will decrease with temperature, causing a full-span output temperature coefficient (fsotc) error. however, if the bridge voltage can be made to increase with temperature at the same rate that tcs decreases with temperature, the fso will remain constant. fsotc compensation is accomplished by resistor r ftc and the fsotc dac, which modulate the excita- tion reference current at isrc as a function of tempera- ture (figure 2). fso dac sets v isrc and remains constant with temperature while the voltage at fsotc varies with temperature. fsotc is the buffered output of the fsotc dac. the reference dac voltage is v bdrive , which is temperature dependent. the fsotc dac alters the tempco of the current source. when the tempco of the bridge voltage is equal in magnitude and opposite in polarity to the tcs, the fsotc errors are compensated and fso will be constant with tempera- ture. offset tc compensation compensating offset tc errors involves first measuring the uncompensated offset tc error, then determining what percentage of the temperature-dependent voltage v bdrive must be added to the output summing junction to correct the error. use the offset tc dac to adjust the amount of bdrive voltage that is added to the output summing junction (figure 3). analog signal path the fully differential analog signal path consists of four stages: ? front-end summing junction for coarse offset correction ? 3-bit pga with eight selectable gains ranging from 41 through 230 ? three-input-channel summing junction ? differential to single-ended output buffer with rail-to- rail output (figure 3) coarse offset correction the sensor output is first fed into a differential summing junction (inm (negative input) and inp (positive input)) with a cmrr > 90db, an input impedance of approxi- mately 1m ? , and a common-mode input voltage range from v ss to v dd . at this summing junction, a coarse off- set-correction voltage is added, and the resultant volt- 2-wire, 4?0ma smart signal conditioner 6 _______________________________________________________________________________________ voltage (v) pressure p min p max full-scale (fs) 4.5 0.5 full-span output (fso) offset figure 1. typical pressure-sensor output
age is fed into the pga. the 3-bit (plus sign) input- referred offset dac (iro dac) generates the coarse offset-correction voltage. the dac voltage reference is 1.25% of v dd ; thus, a v dd of 5v results in a front-end offset-correction voltage ranging from -63mv to +63mv, in 9mv steps (table 1). to add an offset to the input signal, set the iro sign bit high; to subtract an offset from the input signal, set the iro sign bit low. the iro dac bits (c2, c1, c0, and iro sign bit) are pro- grammed in the configuration register (see internal eeprom section). programmable-gain amplifier the programmable-gain amplifier (pga), which is used to set the coarse fso, uses a switched-capacitor cmos technology and contains eight selectable gain levels from 41 to 230, in increments of 27 (table 2). the output of the pga is fed to the output summing junc- tion. the three pga gain bits a2, a1, and a0 are stored in the configuration register. output summing junction the third stage in the analog signal path consists of a summing junction for the pga output, offset correction, and the offset tc correction. both the offset and the off- set tc correction voltages are gained by a factor of 2.3 before being fed into the summing junction, increasing the offset and offset tc correction range. the offset sign bit and offset tc sign bit are stored in the configuration register. the offset sign bit determines whether the off- set correction voltage is added to (sign bit is high) or subtracted from (sign bit is low) the pga output. negative offset tc errors require a logic high for the off- set tc sign bit. alternately, positive offset tc errors dic- tate a logic low for the offset tc sign bit. the output of the summing junction is fed to the output buffer. max1459 2-wire, 4?0ma smart signal conditioner _______________________________________________________________________________________ 7 figure 2. bridge excitation circuit v dd aa 12i isrc = i bdrive i = i isrc i src fsotc r isrc bdrive v dd r ftc external sensor fso dac fsotc dac sotc bdrive 1.25% v dd soff a2 inp inm a1 a0 pga a = 1 out a = 2.3 a = 2.3 offtc dac iro dac v dd offset dac figure 3. signal-path block diagram
max1459 output buffer the output buffer (out) can swing within 50mv of the supply rails with no load, or within 0.25v of either rail while driving a 10k ? load. out can easily drive 0.1? of capacitance. the output is current limited and can be shorted to either v dd or v ss indefinitely. if cs is brought low, out goes high impedance, resulting in typical output impedance of 1m ? . this feature allows parallel max1459 connections, reducing test system wire harness complexity. bridge drive fine fso correction is accomplished by varying the sensor excitation current with the 12-bit fso dac (figure 2). sensor bridge excitation is performed by a programmable current source capable of delivering up to 2ma. the reference current at isrc is established by resistor r isrc and by the voltage at node isrc (con- trolled by the fso dac). the reference current flowing through this pin is multiplied by a current mirror (aa ? 12) and then made available at bdrive for sensor exci- tation. modulation of this current with respect to tem- perature can be used to correct fsotc errors, while modulation with respect to the output voltage (v out ) can be used to correct fso linearity errors. voltage drive sensor for sensors with negligible fsotc, the max1459 can be configured as a fixed-voltage drive by shorting isrc and bdrive. offset tc can then be compensated with r temp . set configuration register bit 5 to 1, and con- nect tempin to a temperature-dependent voltage source. this source can easily be generated by induc- ing a current through r temp . for more information on this application, refer to the max1459 reference man- ual. digital-to-analog converters the four 12-bit, sigma-delta dacs typically settle in less than 100ms. the four dacs have a corresponding memory register in eeprom for storage of correction coefficients. the fso dac takes its reference from v dd and con- trols v isrc , which sets the baseline sensor excitation current. the fso dac is used for fine adjustments to the fso. the offset dac also takes its reference from v dd and provides a 1.22mv resolution with a v dd of 5v. the output of the offset dac is fed into the output summing junction where it is gained by approximately 2.3, which increases the resulting output-referred off- set-correction resolution to 2.8mv. both the offset tc and fsotc dacs take their refer- ences from a temperature-dependent voltage. in default mode, this voltage is internally connected to bdrive. alternatively, a different temperature sensor can be used through tempin by setting bit 5 of the configuration register. this temperature sensor can be either r temp or an external temperature resistor. 2-wire, 4?0ma smart signal conditioner 8 _______________________________________________________________________________________ 2.070 230 1 1 1 7 1.827 203 0 1 1 6 1.584 176 1 0 1 5 1.341 149 0 0 1 4 1.098 122 1 1 0 3 0.855 95 0 1 0 2 0.612 68 1 0 0 1 0.369 output- referred iro dac step size (v dd = 5v) (v) 41 pga gain (+v/+v) 0 pga value a0 a2 0 0 0 a1 table 2. pga gain settings and iro dac step size 0 0 -63 -1.25 1 1 1 0 -7 -54 -1.08 0 1 1 0 -6 -45 -0.90 1 0 1 0 -5 -36 -0.72 0 0 1 0 -4 -27 -0.54 1 1 0 0 -3 -18 -0.36 0 1 0 0 -2 -9 -0.18 1 0 0 0 -1 0 0 0 0 -0 +9 +0.18 1 0 0 1 +1 +18 +0.36 0 1 0 1 +2 +27 +0.54 1 1 0 1 +3 +36 +0.72 0 0 1 1 +4 +45 +0.90 1 0 1 1 +5 +54 +1.08 0 1 1 1 +6 value c0 c2 c1 sign +63 offset correc- tion at v dd = 5v (mv) +1.25 offset correc- tion percent of v dd (%) 1 iro dac 1 1 1 +7 table 1. input-referred offset dac correction values
the offset tc dac output is fed into the output sum- ming junction where it is gained by approximately 2.3, thereby increasing the offset tc correction range. the buffered fsotc dac output is available at fsotc and is connected to isrc via r ftc to correct fsotc errors. internal resistors the max1459 contains three internal resistors (r isrc , r ftc , and r temp ) optimized for common silicon prts. r isrc (in conjunction with the fso dac) programs the nominal sensor excitation current. r ftc (in conjunction with the fsotc dac) compensates the fsotc errors. both r isrc and r ftc have a nominal value of 100k ? . if external resistors are used, r isrc and r ftc can be disabled by setting the appropriate bit (address 07h reset to zero) in the configuration register (table 3). r temp is a high-tempco resistor with a tc of +4600ppm/? and a nominal resistance of 100k ? at +25?. this resistor can be used with certain sensor types that require an external temperature sensor. the two r temp terminals are available as pin 16 and pin 17 of the max1459. internal eeprom the max1459 has a 128-bit internal eeprom arranged as eight 16-bit registers. the 4 uppermost bits for each register are reserved. the internal eeprom is used to store the following (also shown in the memory map in table 4): ? configuration register (table 3) ? 12-bit calibration coefficients for the offset and fso dacs ? 12-bit compensation coefficients for the offset tc and fsotc dacs ? two general-purpose registers available to the user for storing process information such as serial num- ber, batch date, and check sums the eeprom is bit addressable. program the eeprom using the following steps, where the bits have address- es from 0 to 127 (07f hex): 1) read the entire eeprom, and temporarily store the reserved bits. 2) erase the entire eeprom, which causes all bits to be 0 (see the erase eeprom command section). 3) program 1 to the required bits, including the reserved bits (see the write eeprom bit command section). 4) read the whole eeprom, either with the read eep- rom bit or with the read eeprom matrix com- mands (see the read eeprom bit command and read eeprom matrix command sections). configuration register the configuration register (table 3) determines the pga gain, the polarity of the offset and offset tc coeffi- cients, and the coarse offset correction (iro dac). it also enables/disables internal resistors (r ftc and r isrc ). dac registers the offset, offset tc, fso, and fsotc registers store the coefficients used by their respective calibration/ compensation dacs. detailed description of the digital lines chip-select (cs) and write-enable (we) cs is used to enable out, control serial communica- tion, and force an update of the configuration and dac registers: ? a low on cs disables serial communication and places out in a high-impedance state. ? a transition from low to high on cs forces an update of the configuration and dac registers from the max1459 2-wire, 4?0ma smart signal conditioner _______________________________________________________________________________________ 9 table 3. configuration register description 01 1 00 03 0 3 02 2 05 5 04 07 4 7 06 6 09 bit 9 eeprom address (hex) 08 0b 8 11 0a 10 offset tc sign bit, sotc offset sign bit, soff pga gain (lsb), a0 pga gain, a1 pga gain (msb), a2 temperature sensor selection bit (0 = default v bdrive ) reserved ? r isrc /r ftc selection bit (0 = enable internal), irs iro lsb, c0 iro, c1 iro msb, c2 iro sign, s iro description configuration register
max1459 eeprom when the u bit of the init sequence is zero. ? a transition from high to low on cs terminates pro- gramming mode. ? a logic high on cs enables out and serial commu- nication (see communication protocol section). we controls the refresh rate for the internal configura- tion and dac registers from the eeprom and enables the erase/write operations. if communication has been initiated (see communication protocol section), internal register refresh is disabled. ? a low on we disables the erase/write operations and also disables register refreshing from the eeprom. ? a high on we selects a refresh rate of approximately 400 times per second and enables eeprom erase/write operations. ? it is recommended that we be connected to v ss after the max1459 eeprom has been programmed. sclk (serial clock) sclk must be driven externally and is used to input commands to the max1459 or program the internal eeprom contents. input data on dio is latched on the rising edge of sclk. 2-wire, 4?0ma smart signal conditioner 10 ______________________________________________________________________________________ table 4. eeprom memory map ee address contents ee address contents ee address contents ee address contents ee address contents reserved ee address contents ee address contents 0e 0 0c 0 0f 0d 0 0a 08 0b 09 06 04 07 05 02 1 00 configuration 03 01 1e 0 1c 1 1f 1d 0 1a 18 1b 19 16 14 17 15 12 1 10 msb offset lsb 13 11 2e 0 2c 0 2f 2d 1 2a 28 2b 29 26 24 27 25 22 1 20 msb offset tc lsb 23 21 3e 0 3c 1 3f 3d 1 3a 38 3b 39 36 34 37 35 32 1 30 msb fso lsb 33 31 4e 1 4c 0 4f 4d 0 4a 48 4b 49 46 44 47 45 42 1 40 msb fsotc lsb 43 41 6e 0 6c 0 6f 6d 0 6a 68 6b 69 66 64 67 65 62 0 60 user-defined bits 63 61 7e 0 7c 0 7f 7d 0 7a 78 7b 79 76 74 77 75 72 0 70 user-defined bits 73 71 note: the max1459 processes the reserved bits in the eeprom. if these bits are not properly programmed, the configuration and dac registers will not be updated correctly. = reserved bits 51 53 50 0 52 55 57 54 56 59 5b 58 5a 0 5d 5f 0 5c 0 5e reserved
data input/output the dio line is an input/output pin used to issue com- mands to the max1459 (input mode) or read the eeprom contents (output mode). in input mode (the default mode), data on dio is latched on each rising edge of sclk. therefore, data on dio must be stable at the rising edge of sclk and should transition on the falling edge of sclk. dio will switch to output mode after receiving either the read eeprom command or the read eeprom matrix command. see the read eeprom section for detailed information. communication protocol to initiate communication, the first 8 bits on dio after cs transitions from low to high must be 101010u0 (aa hex or a8 hex, defined as the init sequence). the max1459 will then begin accepting 16-bit control words (figure 4). if the init sequence is not detected, all subsequent data on dio is ignored until cs again transitions from low to high and the correct init sequence is received. the u bit of the init sequence controls the updating of the dacs and configuration register from the internal eeprom. if this bit is low (u = 0, init sequence = a8 hex), all four internal dacs and the configuration regis- ter will be updated from the eeprom on the next rising edge of cs (this is also the default on power-up). if the u bit is high (init sequence = aa hex), the dacs and configuration register will not be updated from the internal eeprom; they will retain their current value on any subsequent cs rising edge. the max1459 contin- ues to accept control words until cs is brought low. control words after receiving the init sequence on dio, the max1459 begins latching in 16-bit control words, msb first (figure 5). the first 4 bits of the control word (the msbs, cm3?m0) are the command field. the last 12 bits (d11?0) represent the data field. the max1459 sup- ports the commands listed in table 5. no-op command (0 hex) the no-operation (no-op) command must be issued before and after the commands erase eeprom and write eeprom bit. in the case of the erase eep- rom command, the control word must be 0000 hex. in the case of the write eeprom bit command, the command field must be 0h, and the data field must have, in its lower bits, the eeprom address to be writ- ten (figure 6). for example, to write location 1c hex of max1459 2-wire, 4?0ma smart signal conditioner ______________________________________________________________________________________ 11 figure 5. control-word timing diagram sclk dio command msb lsb lsb msb msb lsb data 16-bit control word d9 d6 d8 d5 d7 d4 d3 d2 d1 d0 cm3 cm0 cm2 d11 cm1 d10 figure 4. communication sequence cs sclk dio t min = 1.5ms 16 clk cycles init sequence control word control word control words 16 clk cycles n x 16 clk cycles x 1 0 1 cm3 cm3 cm2 cm2 do do 0u0 1 0 8 clk cycles
max1459 the eeprom (one of the reserved bits), the necessary commands are: 001c hex: no-op command, with address 1c hex in the data field 201c hex: write eeprom bit command, with address 1c hex in the data field 001c hex: no-op command, with address 1c hex in the data field erase eeprom command (1 hex) when an erase eeprom command is issued, all of the memory locations in the eeprom are reset to a logic 0. the data field of the 16-bit word is ignored (figure 7). important: an internal charge pump develops voltages greater than 20v for eeprom programming operations. the eeprom control logic requires 10ms to erase the eeprom. after sending a write or erase command, fail- ure to wait 10ms before issuing another command may result in unreliable eeprom operation. the maximum number of eeprom erase cycles should not ex- ceed 100. write eeprom bit command (2 hex) the write eeprom bit command stores a logic high at the memory location specified by the lower 7 bits of the data field (d6?0). the higher bits of the data field (d11?7) are ignored (figure 8). note that to write to the internal eeprom, we and cs must be high. in 2-wire, 4?0ma smart signal conditioner 12 ______________________________________________________________________________________ load register 1 1 fh 1 1 read eeprom matrix 1 1 eh 1 0 control output mux 1 0 dh 1 1 write data to fsotc dac 1 0 ch 1 0 no-op 0 0 0h 0 0 erase eeprom 0 0 1h 0 1 write eeprom bit 0 1 2h 0 0 read eeprom bit 0 1 3h 0 1 maxim reserved 1 0 4h 0 0 maxim reserved 1 0 5h 0 1 maxim reserved 1 1 6h 0 0 maxim reserved 1 1 7h 0 1 write data to configuration register 0 0 8h 1 0 write data to offset dac 0 0 9h 1 1 write data to offset-tc dac 0 1 ah 1 0 write data to fso dac 0 1 bh 1 1 function cm2 cm1 hex code cm3 cm0 figure 7. erase eeprom command timing diagram sclk dio command msb lsb lsb msb msb lsb data 16-bit control word - erase eeprom command (1xxx hex) x x x x x x xxx x 0 1 0 x 0 x figure 6. no-op command timing diagram sclk dio command msb lsb lsb msb msb lsb data 16-bit control word - no-op command (ooxx hex) 0 a6 0 a5 0 a4 a3 a2 a1 a0 0 0 0 0 0 0 table 5. max1459 commands
addition, the eeprom should only be written to at t a = +25? and v dd = +5v. writing to the internal eeprom is a time-consuming process and should only be done once. all calibra- tion/compensation coefficients are determined by writ- ing directly to the configuration and dac registers. use the following procedure to write these calibration/com- pensation coefficients to the eeprom: 1) initiate the no-op command (0000 hex). 2) initiate the erase eeprom command (1000 hex). 3) wait 10ms. 4) initiate the no-op command (0000 hex). 5) initiate the no-op command, with address of bit in the data field (00xx hex), where xx is the bit address in the data field. 6) initiate the write eeprom bit command, with the same bit address in the data field (20xx hex). 7) wait 10ms. 8) initiate the no-op command, with the same bit address in the data field (00xx hex). 9) return to step 5 until all necessary bits have been set. 10) read eeprom to verify that the correct calibration/ compensation coefficients have been stored. read eeprom bit command (3 hex) the read eeprom bit command returns the bit stored at the memory location addressed by the lower 7 bits of the data field (d6?0). the higher bits of the data field are ignored. note that after a read command has been issued, the dio lines become an output and the contents of the addressed eeprom location will be available on dio for the next 15 cycles of sclk. on the falling edge of the 16th sclk cycle after issuing the read eeprom command, dio returns to input mode (figure 9). dio is stable on the rising edge of sclk. writing to the configuration, dac, and output select registers (commands 8, 9, a, b, c, and d hex) commands 8 hex, 9 hex, a hex, b hex, and c hex write the 12 bits of the data field (d11?0) directly to the configuration and dac registers. these commands must be followed by the load register command (fxxx hex). note that all four dacs and the configura- tion register can be updated without toggling the cs line after a valid init sequence (figure 10). output select command (d hex) the output select command switches the output pin to other internal nodes instead of the default pga output (figure 10). table 6 lists the output mux settings. max1459 2-wire, 4?0ma smart signal conditioner ______________________________________________________________________________________ 13 figure 8. write eeprom bit command timing diagram sclk dio command msb lsb lsb msb msb lsb data 16-bit control word - write eeprom bit command (20xx hex) 0 a6 0 a5 0 a4 a3 a2 a1 a0 0 0 0 0 1 0 figure 9. timing diagram for read eeprom bit sclk dio command msb lsb lsb msb msb lsb data 16-bit control word - read eeprom bit command (30xx hex) 0 d6 0 d5 0 d4 d3 d2 d1 d0 0 1 0 0 1 0 16 clock cycles 15 clock cycles 16 clock cycles dio is an output pin x cm3 cm2 d0 ee bit data control word
max1459 the output mux facilitates the test system to monitor dif- ferent voltages through the output pin. read eeprom matrix command (e hex) the contents of the entire 128-bit eeprom is available on dio upon issuing this command. once the max1459 receives the read eeprom matrix com- mand, dio turns into an output for the next 128 clock cycles. after the 128th clock cycle, dio returns to its default input mode and the max1459 is ready to accept new commands (figure 11). data on dio changes on falling edges of sclk and is stable on ris- ing edges of sclk. the eeprom data on dio is eight 16-bit words, msb to lsb. the sequence is then 0f hex, 0e hex, 0d hex, ? 00 hex (word 0), 1f hex, 1e hex, 1d hex, ?(word 1), ? 7f hex, 7e hex, ? 70 hex (word 7). __________applications information power-up at power-up, the following occurs: 1) the dac and configuration registers are reset to zero. 2) cs transitions from low to high after power-up (an internal pull-up resistor ensures that this happens if cs is left unconnected), and the eeprom contents are read and processed. 3) the dac and configuration registers are updated either once (if we is logic 0) or approximately 400 times per second (if we is logic 1). 4) the max1459 begins accepting commands in a ser- ial format on dio immediately after receiving the init sequence command. the max1459 must be programmed for proper opera- tion. compensation procedure the following compensation procedure was used to obtain the results shown in table 7 and figure 12. it assumes a pressure transducer with a +5v supply and an output voltage that is ratiometric to the supply volt- age. the desired offset voltage (v out at p min ) is 0.5v, and the desired fso voltage (v out(p max ) - v out(p min ) ) is 4v; thus, the fso voltage (v out at p max ) will be 4.5v (figure 1). the procedure requires a minimum of two 2-wire, 4?0ma smart signal conditioner 14 ______________________________________________________________________________________ sclk dio command msb lsb lsb msb msb lsb data 8 hex, 9 hex, a hex, b hex, c hex, or d hex write register command d9 d6 d8 d5 d7 d4 d3 d2 d1 d0 cm3 cm0 cm2 d11 cm1 d10 command data x x x x x x xxx x 1 1 1 x 1 x msb lsb 16 bit control word - load register command (fxxx hex) figure 10. timing diagram for write register operations mux value d1 d0 output 0 (default power-up) 0 0 conditioned output voltage (pga) 1 0 1 sensor bridge voltage (v b ) 2 1 0 current-source voltage (v span ) 3 1 1 power supply voltage (v dd ) table 6. output mux selection sclk dio command msb lsb lsb msb msb lsb data 16-bit control word - read eeprom matrix command (exxx) x x x x x x xxx x 1 0 1 x 1 x 2f 20 2e 7f 7e 70 cm3 cm2 d0 0f 1f 0e 1e 00 10 16 clock cycles 16 clock cycles dio is an output pin for 128 clock cycles 16 clock cycles 16 clock cycles 16 clock cycles word 0 msb lsb msb word 1 lsb msb word 2 lsb msb word 7 lsb control word figure 11. timing diagram for reading the entire eeprom content
test pressures (e.g., zero and full scale) at two arbitrary test temperatures, t 1 and t 2 . ideally, t 1 and t 2 are the two points where we wish to perform best linear fit com- pensation. the following outlines a typical compensa- tion procedure: 1) perform coefficient initialization. 2) perform fso calibration. 3) perform fsotc compensation. 4) perform offset tc compensation. 5) perform offset calibration. coefficient initialization select the resistor values and the pga gain to prevent overload of the pga and bridge current source. determine whether the max1459? internal resistors are suitable or external resistors are necessary. these val- ues depend on sensor behavior and require some sen- sor characterization data, which may be available from the sensor manufacturer. if not, the data can be gener- ated by performing a two-temperature, two-pressure sensor evaluation. the required sensor information is shown in table 8 and can be used to obtain the values for the parameters listed in table 9. selecting r isrc when using an external resistor, use the equation below to determine the value of r isrc , and place the resistor between isrc and v ss . since the 12-bit fso dac pro- vides considerable dynamic range, the r isrc value need not be exact. generally, any resistor value within ?0% of the calculated value is acceptable. if both the internal resistors r isrc and r ftc are used, set the irs bit at eeprom address bit 07 hex low. max1459 2-wire, 4?0ma smart signal conditioner ______________________________________________________________________________________ 15 -20 -10 10 0 20 30 -50 0 50 100 150 uncompensated sensor error temperature ( c) error (% fso) offset fso -0.8 -0.6 0.4 -0.2 -0.4 0 0.2 0.6 0.8 -50 0 50 100 150 compensation transducer error temperature (c) error (% span) offset fso figure 12. comparison of an uncalibrated sensor and a temperature-compensated transducer table 7. max1459 calibration and compensation 0.7% fso -40? to +125? temperature range 0.5% fso fso tc nonlinearity -35% fso fso tc offset tc nonlinearity -17% fso offset tc +15mv/v fso ?0% fso offset description name typical uncompensated input (sensor) ?0mv (?.5% fso) fso accuracy over temp range ?8mv (?.7% fso) offset accuracy over temp range 4.000v ?mv fso at +25? 0.500v ?mv offset at +25? ratiometric to v dd at 5.0v description name v out typical compensated transducer output
max1459 otherwise, set irs high and connect external resistors as shown in figure 13: where rb(t) is the sensor input impedance at tempera- ture t1 (+25? in this example). selecting r ftc when using an external resistor, use the equation below to determine the value for r ftc , and place the resistor between isrc and fsotc. since the 12-bit fsotc dac provides considerable dynamic range, the r ftc value need not be exact. generally, any resistor value within ?0% of the calculated value is accept- able: this approximation works best for bulk, micromachined, silicon prts. negative values for r ftc indicate uncon- ventional sensor behavior that can be compensated by the max1459 with additional external circuitry. selecting the pga gain setting to select the pga gain setting, first calculate sensorfso, the sensor full-span output voltage at t1: sensorfso = s x v bdrive x ? p = +1.5mv/v per psi x 2.5v x 10 psi = 0.0375v where s is the sensor sensitivity at t1, v bdrive is the sensor excitation voltage (initially 2.5v), and ? p is the maximum pressure differential. then calculate the ideal gain using the following formula, and select the nearest gain setting from table 2: where outfso is the desired calibrated transducer full-span output voltage, and sensorfso is the sensor full-span output voltage at t1. in this example, a pga value of 2 (gain of +95v/v) is the best selection. determining input-referred offset the input-referred offset (iro) register is used to null any front-end sensor offset errors prior to amplification by the pga. this reduces the possibility of saturating the pga and maximizes the useful dynamic range of the pga (particularly at the higher gain values). a outfso sensorfso 4v 0.0375v +106v/v pga ?= r r 500ppm/ c 60k 500ppm/ c 60k ftc isrc ? ? ?? tcr - tcs 2600ppm/ c - -2100ppm/ c || || ? r rb(t kk isrc ? ? ) 12 12 5 60 ?? 2-wire, 4?0ma smart signal conditioner 16 ______________________________________________________________________________________ internal (approximately 100k ? ) or user- supplied resistor that compensates fsotc errors r ftc fsotc compensation dac fsotc coef fso trim dac fso coef offset tc sign bit offtc sign offset tc compensation dac coefficient offtc coef offset sign bit off sign offset correction dac coefficient off coef internal resistor selection bit irs input-referred offset sign bit parameter iro sign description input-referred offset correction dac value internal (approximately 100k ? ) or user- supplied resistor that programs the nomi- nal sensor excitation current iro r isrc programmable-gain amplifier gain a pga table 9. compensation components and values maximum input pressure p max 10 psi minimum input pressure p min sensitivity linearity error as % fso, bslf (best straight-line fit) 0 psi s(p) 0.1% fso, bslf offset tempco otc offset -1000ppm/? of fso o(t) +12mv/v at +25? sensitivity tempco tcs sensitivity -2100ppm/? s(t) +1.5mv/v per psi at +25? parameter bridge impedance tempco sensor description tcr bridge impedance 2600ppm/? rb(t) typical values 5k ? at +25? table 8. sensor information for typical prt
first, calculate the ideal iro correction voltage using the following formula, and select the nearest setting from table 1: where iroideal is the exact voltage required to perfect- ly null the sensor, o(t1) is the sensor offset voltage in v/v at +25?, and v bdrive (t1) is the nominal sensor excitation voltage at +25?. in this example, 30mv must be subtracted from the amplifier front end to null the sensor perfectly. from table 1, select an iro value of 3 to set the iro dac to 27mv, which is nearest the ideal value. to subtract this value, set the iro sign bit to 0. the residual output-referred offset error will be corrected later with the offset dac. determining offtc coef initial value generally, offtc coef can initially be set to 0 since the offset tc error will be compensated in a later step. however, sensors with large offset tc errors may require an initial coarse offset tc adjustment to prevent the pga from saturating during the compensation pro- cedure as temperature is increased. an initial coarse offset tc adjustment is required for sensors with an off- set tc greater than about 10% of the fso. if an initial coarse offset tc adjustment is required, use the follow- ing equation: offtc coef 4096 v t v t 2.3 4096 otc fso tcs v 2.3 4096 -1000ppm/ c 4v -2100ppm/ c 2.5v 2.3 out bdrive bdrive = () () ? () ? () ? x x xx xt xxxt xx xx ? ? ? ? 1357 iroideal - o t1 v t1 - 0.012v/v 2.5v - 30mv bdrive = () () [] = () = x x max1459 2-wire, 4?0ma smart signal conditioner ______________________________________________________________________________________ 17 max1459 12-bit d/a - offset tc 12-bit d/a - offset configuration register 12-bit d/a - fso coarse offset (iro dac) 12-bit d/a - fsotc fsotc r nbias = 402k 1% a = 1 v ss +5v out v dd digital interface pga cs we sclk dio bdrive inm isrc inp c2 0.1 f c1 0.1 f v ss r isrc r ftc r isrc r ftc 128-bit eeprom v dd sensor select output ampout amp- amp+ r temp temp1 temp2 tempin nbias figure 13. basic ratiometric output configuration
max1459 2-wire, 4?0ma smart signal conditioner 18 ______________________________________________________________________________________ where otc is the sensor offset tc error as a ppm/? of outfso (table 8), ? t is the operating temperature range in ?, and offtc coef is the numerical decimal value to be loaded into the dac. for positive values, set the offtc sign bit high; for negative values, set the offtc sign bit low. if the absolute value of the offtc coef is larger than 4096, the sensor has a very large offset tc error, which the max1459 is unable to com- pletely correct without the use of a temperature sensor. fso calibration perform fso calibration at room temperature with a full- scale sensor excitation: 1) set fsotc coef to 1000. 2) at t1, adjust fso dac until v bdrive is about 2.5v. 3) adjust offset dac (and offset sign bit, if needed) until the t1 offset voltage is 0.5v (see offset calibration section). 4) measure the full-span output (measuredv fso ). 5) calculate the ideal bridge voltage, v bideal (t1), using the following equation: note: if v bideal (t1) is outside the allowable bridge voltage swing of (v ss + 1.3v) to (v dd - 1.3v), readjust the pga gain setting. if v bideal (t1) is too low, decrease the pga gain setting by one step and return to step 2. if v bideal (t1) is too high, increase the pga gain setting by one step and return to step 2. 6) set v bideal (t1) by adjusting the fso dac. 7) readjust offset dac until the v out = 0.5v (see offset calibration section). three-step fsotc compensation step 1 use the following procedure to determine fsotc coef; four variables, a?, will be used: 1) name the existing fso dac coefficient a. 2) change fsotc dac to 3000. 3) adjust fso dac until v bdrive (t1) is equal to v bideal (t1). 4) name the new fso dac coefficient b. 5) readjust the offset voltage (by adjusting the offset dac), if required, to v out = 0.5v. at this point, it is important that no other changes be made to the offset or offset tc dacs until the offset tc compensation step has been completed. step 2 to complete linear fsotc compensation, take data measurements at a second temperature, t2 . the follow- ing equation and procedure are suitable for any two arbitrary temperatures where t2 > t1. the following steps are performed at temperature t2: 1) measure the full-span output (measuredv fso (t2)). 2) calculate v bideal (t2) using the following equation: 3) set v bideal (t2) by adjusting the fso dac. 4) name the current fso dac coefficient d. 5) change fsotc dac to 1000. 6) adjust fso dac until v bdrive is equal to v bideal (t2). 7) name the fso dac coefficient c. step 3 insert the data previously obtained from steps 1 and 2 into the following equation to compute fsotc coef: 1) load this fsotc coef value into the fsotc dac. 2) adjust the fso dac until v bdrive (t2) is equal to v bideal (t2). this completes both fso calibration and fso tc com- pensation. offset tc compensation the offset voltage at t1 was previously set to 0.5v; therefore, any variation from this voltage at t2 is an offset tc error. perform the following steps: 1) measure the offset voltage at t2. 2) use the following equation to compute the correc- tion required: fsotc coef 1000 b - d 3000 c - a b-d c-a = () + () () + () vt2 v 1 desiredv - measuredv t2 measuredv t2 bideal bdrive fso fso fso () = + () () ? ? ? ? ? ? x vt v 1 desiredv - measuredv t measuredv t bideal bdrive fso fso fso 1 1 1 () = + () () ? ? ? ? ? ? ? ? x
max1459 2-wire, 4?0ma smart signal conditioner ______________________________________________________________________________________ 19 note: currentofftc coef is the current value stored in the offset tc dac. if the offset tc sign bit (sotc) is low, this number is negative. 3) load this value into the offset tc dac. 4) if newofftc coef is negative, set the offset tc sign (sotc) bit low; otherwise, set it high. offset tc compensation is now complete. offset calibration at this point, the sensor should still be at temperature t2. the final offset adjustment can be made at t2 or t1 by adjusting the offset dac (and optionally the offset sign bit, soff) until the output (v out(p min ) ) reads 0.5v at zero input pressure. use the following procedure: 1) set offset dac to zero (offset coef = 0). 2) measure the voltage at out. 3) if v out is greater than the desired offset voltage (0.5v in this example), set soff low; otherwise, set it high. 4) increase offset coef until v out equals the desired offset voltage. offset calibration is now complete. table 7 and figure 12 compare an uncompensated input to a typical com- pensated transducer output. sensor selection silicon piezoresistive sensors the max1459 is optimized for use with sensors designed for current mode operation that have a tcr in the neighborhood of 2000ppm/? or more. voltage- mode excitation sensors have a characteristically low tcr, which may necessitate the use of a temperature sensor (internal or external). for more information on using the max1459 in conditions such as tcr < tcs, low tcs, or low tcr, refer to the max1459 reference manual. the ideal sensor used with the max1459 will not change input impedance as a function of mechani- cal excitation (pressure). prts that are imbalanced behave poorly. strain-gauge sensors the max1459 was optimized for signal conditioning of piezoresistive sensors; however, it offers powerful per- formance for signal conditioning strain-gauge sensors as well. strain-gauge sensors vary greatly in perfor- mance and compensation requirements since they are used to measure many variables (e.g., pressure, accel- eration, force, torque, etc.) and use a variety of materi- als for the sensing element (e.g., constantan, manganin, etc.) and spring elements (e.g., steel, glass, aluminum, etc.). this makes signal conditioning extremely applica- tion dependent. for more information on this applica- tion, refer to the max1459 reference manual. ratiometric output configuration ratiometric output configuration provides an output that is proportional to the power-supply voltage. when used with ratiometric a/d converters, this output provides digital pressure values independent of supply voltage. most automotive and some industrial applications require ratiometric outputs. the max1459 provides a high-performance ratiometric output with a minimum number of external components (figure 13). these external components include the fol- lowing: ? one power-supply bypass capacitor (c1) ? two optional resistors, one from fsotc to isrc, and another from isrc to v ss , depending on the sensor type ? one optional capacitor c2 from bdrive to v ss 2-wire, 4?0ma configuration in the 2-wire configuration, a 4ma current is used to power a transducer, and an incremental current of 0ma to 16ma proportional to the measured pressure is transmitted over the same pair of wires. current output enables long-distance transmission without a loss of accuracy due to cable resistance. only a few components (figure 14) are required to build a 4?0ma output configuration. use a low-quies- cent-current voltage regulator with a built-in bandgap reference (such as the max875). since the max1459 performs temperature and gain compensation of the circuit, the temperature coefficient and the calibration accuracy of the reference voltage are of secondary importance. the max1459 controls the voltage across resistor r sense . with r sense = 50 ? , a 0.2v to 1.0v range would be required during the calibration procedure. resistors r b , r c , and r off are used to set the voltage across r sense . for overvoltage protection, place a zener diode across v in - and v in + (figure 14). a feedthrough capacitor across the inputs reduces emi/rfi. for more information on this application, refer to the max1459 reference manual. in 4?0ma applications, pay close attention to thermal management. q1 will dissipate significant power and, if newofftc coef currentofftc coef - 4096 v t - v t2 2.3 v t - v t2 offset offset bdrive bdrive = () ( ) [] () ( ) [] ? ? ? ? ? ? ? ? 1 1
max1459 placed close to the pressure sensor, can cause exces- sive errors. of particular concern is an extremely long sensor-output settling time. nonlinearity compensation r temp can be used in conjunction with r isrc and rftc to compensate for sensor nonlinearity. for more information on this application, refer to the max1459 reference manual. test system configuration the max1459 is designed to support an automated production pressure-temperature test system with inte- grated calibration and temperature compensation. figure 15 shows the implementation concept for a low- cost test system capable of testing multiple transducer modules connected in parallel. three-state outputs on the max1459 allow for parallel connection of transduc- ers. a digital multiplexer controls the chip-select signal for each transducer. the test system shown in figure 15 includes a dedicated test bus consisting of five wires: ? two power-supply lines ? one analog output voltage line from the transducers to a system dvm ? two serial-interface lines: dio (input/output) and sclk (clock) max1459 evaluation ____________________________________ development kit to expedite the development of max1459-based trans- ducers and test systems, maxim has produced the max1459 evaluation kit (ev kit). first-time users of the max1459 are strongly encouraged to use this kit. the max1459 ev kit is designed to facilitate manu- al programming of the max1459 and includes the fol- lowing: 1) evaluation board with a silicon pressure sensor. 2-wire, 4?0ma smart signal conditioner 20 ______________________________________________________________________________________ max1459 v dd v ss r b r c r d 1f i dd ~ 3ma r off auxiliary op amp (internal to max1459) 0.1f max875 v cc gnd 5v g s d q 2 100 ? pn4391 0.1f 1f c f gnd r sense 50 ? r y b e c 2n2222 q1 r x transzorb v in + 4 20ma 12v 40v ci v in - figure 14. 2-wire, 4?0ma circuit transzorb is a trademark of general semiconductor industries, inc.
2) max1459 reference manual, which describes in detail the architecture and functionality of the max1459. this manual was developed for test engi- neers familiar with data acquisition of sensor data and provides sensor compensation algorithms and test procedures. 3) max1459 communication software, which enables programming of the max1459 from a computer (ibm compatible), one module at a time. 4) interface adapter and cable, which allow the con- nection of the evaluation board to a pc parallel port. max1459 pilot production system maxim understands that one of the biggest challenges in pressure sensor design is the transition from proto- type to production. to simplify this transition, maxim has developed the fully automated pilot production system for volume applications. the system consists of the maxim 14xxdasboard plus one or more 14xxmuxboard modules, a dvm, an environmental chamber, and a pressure controller. only the 14xxdasboard and the 14xxmuxboard modules are available through maxim. the dvm, envi- ronmental chamber, and pressure controller must be acquired through other vendors. the 14xxdasboard, in conjunction with the 14xxmuxboard modules, allow compensation of up to 112 units. ieee-488 commands select the active dut and communicate with the max14xx application cir- cuits. all system voltage measurements are multiplexed for use with a single external dvm. each dut interfaces to the 14xxmuxboard by means of a general-purpose transition board, which provides digital interface signals and low-noise analog inputs. the 14xxdasboard is required to operate the 14xxmuxboard. all driver soft- ware is incorporated into the 14xxdasboard firmware. sensor compensation procedure is implemented using national instruments?labview program. max1459 2-wire, 4?0ma smart signal conditioner ______________________________________________________________________________________ 21 max1459 dio out v dd cs module 1 sclk v ss v ss v dd v dd v ss test oven max1459 dio out cs module 2 sclk dio vout digital multiplexer +5v cs[1:n] cs1 bdrive inp inm bdrive inp inm bdrive inp inm cs2 csn sclk max1459 dio out cs module n sclk dvm figure 15. automated test system concept labview is a trademark of national instruments.
max1459 you may have to adapt various portions of the com- pensation procedure if you are using a different pres- sure controller, oven, or dvm than what the system was designed to accommodate. contact factory for pricing and availability. customization maxim can customize the max1459 for high-volume applications. with a dedicated cell library consisting of more than 200 sensor-specific functional blocks, maxim can quickly provide customized max1459 solutions. please contact maxim for further information. 2-wire, 4?0ma smart signal conditioner 22 ______________________________________________________________________________________ functional diagram max1459 12-bit d/a - offset tc 12-bit d/a - offset configuration register 12-bit d/a - fso coarse offset (iro dac) 12-bit d/a - fsotc fsotc nbias a = 1 out v dd digital interface pga cs we sclk dio bdrive inm isrc inp v ss r isrc r ftc 128-bit eeprom v dd output select ampout amp- amp+ r temp temp1 temp2 tempin v ss chip information transistor count: 7792 substrate connected to v ss
max1459 2-wire, 4?0ma smart signal conditioner ______________________________________________________________________________________ 23 package information ssop.eps
max1459 2-wire, 4?0ma smart signal conditioner maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2000 maxim integrated products printed usa is a registered trademark of maxim integrated products. notes

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